RTL Design & Verification Member
Apr 2026 – Present10 Gb/s Ethernet PCS · 64b/66b encoding · RTL verification
I’m Armaan, a Nanotechnology Engineering student at the University of Waterloo
.
I’m interested in digital hardware, computer architecture, and verification.
I’ve worked on electrical design at 
and RTL design and verification with UWASIC.
Experience
UWASIC
Design Engineering Intern
May 2026 – Aug 2026Pickering refurbishment · Design reviews · Engineering change control
Selected projects
In progress
L1 cache controller
A 1 KB direct-mapped cache design exploring address decoding, tag comparison, and cache refills.
CPUL1 CACHEtag / index / offsetMEMORY
Parameterized synchronous FIFO
Configurable data width and depth, circular pointers, occupancy tracking, and full/empty flags.
SPI-controlled PWM peripheral
An SPI Mode 0 peripheral with memory-mapped control of 16 digital outputs and 16 PWM channels.
Python RTL regression tool
JSON-configured RTL simulations with automated compilation and consolidated pass/fail reports.